Senior EM/IR Engineer

WHAT YOU WILL BE DOING:

Lead EM/IR drop analysis for complex SoC designs at block and full-chip levels across all process corners

Define and implement power delivery network (PDN) strategy to meet EM/IR sign-off requirements

Perform static and dynamic IR-drop analysis and work with physical design teams to implement power grid improvements

Analyze electromigration violations and develop mitigation strategies for metal and via connections

Collaborate with physical design engineers to optimize power grid density, via stacking, and decap placement

Develop and maintain EM/IR analysis flows, scripts, and automation infrastructure

Work with foundry design rules and reliability specifications to ensure sign-off compliance

Define power intent (UPF/CPF) requirements and validate implementation against power management intent

Provide power analysis results and recommendations to design leadership and cross-functional teams

Document EM/IR methodology guidelines, best practices, and sign-off reports

WHAT YOU BRING TO THIS ROLE:

Minimum 8+ years of experience in EM/IR analysis and power integrity for complex ASICs or SoCs

Hands-on proficiency with industry-standard EM/IR tools such as Cadence Voltus, Synopsys RedHawk, or equivalent

Deep understanding of power delivery network design, power grid analysis, and IR-drop mitigation techniques

Strong knowledge of electromigration physics, EM rules, and reliability analysis methodologies

Experience with both static and dynamic power analysis including vectorless and vector-based approaches

Solid understanding of low-power design techniques and their interaction with power integrity

Proficiency in scripting (Tcl, Python) for EM/IR flow development and result automation

Familiarity with advanced process node design rules and foundry reliability specifications

Excellent ability to communicate complex analysis results clearly to cross-functional teams

BONUS POINTS:

Experience with 7nm or sub-7nm EM/IR sign-off requirements

Exposure to thermal analysis and electro-thermal co-simulation

Familiarity with package-level power integrity and chip-package co-design

Experience with advanced power management architectures (DVFS, multiple voltage domains, retention)

Background in satellite communication, 5G, or high-reliability IoT chip design