Senior Physical Design Engineer
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Some ghost-posting signals
- open for 86 days (60–89 days is elevated risk)
- 123 open roles at this company in 30 days (mass-hiring blitz)
- no salary disclosed (correlates with ghost postings)
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About the role
WHAT YOU WILL BE DOING:
Lead physical design implementation from floorplanning through GDSII sign-off for complex SoC blocks and full-chip designs
Perform floorplanning, power planning, placement, clock tree synthesis (CTS), and routing
Drive physical design closure meeting PPA (Power, Performance, Area) targets across all design corners
Collaborate with the STA team to analyze and resolve timing violations through ECO-driven optimization
Conduct and resolve physical verification (DRC, LVS, ERC) issues in partnership with the signoff team
Develop and maintain physical design scripts, flows, and automation in Tcl/Python
Work with foundry process design kits (PDKs) and ensure design rule compliance on advanced nodes
Support integration of hard macros, memory compilers, and analog IP into top-level designs
Analyze and optimize signal integrity, including crosstalk and noise effects
Contribute to physical design methodology development and mentor junior engineers
WHAT YOU BRING TO THIS ROLE:
Minimum 8+ years of experience in physical design of complex digital ASICs or SoCs
Deep expertise in Cadence Innovus, with broad familiarity with other P&R tools such as Synopsys ICC2
Strong experience in floorplanning, power planning, placement, CTS, and routing for multi-million gate designs
Deep knowledge of timing-driven physical design and working with STA engineers for timing closure
Experience with physical verification tools (Mentor Calibre, Synopsys ICV) and DRC/LVS debug
Proficiency in scripting (Tcl, Python) for flow development and automation
Solid understanding of low-power design techniques (clock gating, power domains, UPF/CPF)
Experience with advanced process nodes and associated PDK constraints
Strong problem-solving skills and attention to detail in a deadline-driven environment
BONUS POINTS:
Experience with 7nm or sub-7nm process nodes
Exposure to custom digital or mixed-signal IC physical design
Familiarity with signal integrity analysis tools and methodology
Experience with hierarchical physical design flows for very large SoCs
Background in satellite, 5G, or IoT chip design
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