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Staff FPGA Engineer (DSP)

espace Saratoga, CA

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Ghost-risk verdict

Some ghost-posting signals

  • open for 315 days (90+ without a fill is a strong ghost signal)
  • 123 open roles at this company in 30 days (mass-hiring blitz)
  • no salary disclosed (correlates with ghost postings)

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About the role

What you will do:

The functions of this role include providing strategic direction and implementation in the following areas:

Own FPGA RTLdevelopmentin either SystemVerilog or VHDL from blank sheet to flight.

Develop FPGA logical architecture and requirements in collaboration with other engineering disciplines including defining HW/SW interfaces between fabric logic and processing subsystems.

Implement a digital channelizer beamformer from bit-accurate reference models

Drive part selection and define PCB architecture

Perform design verification including simulations, test benches, timing analysis, and hardware testing.

Lead design reviews, demonstrate requirement traceability, and create documentation for FPGA operation and interfacing with other SW and FPGA systems.

Develop and participate in test campaigns ranging from unit level manual tests, unit automated tests, and system level tests.

What you bring to this role:

10+ years of experience in FPGA RTL architecture, development, verification, deployment, and maintenance.

Skilled at SystemVerilog or VHDL.

Skilled in at least 1 scripting language (TCL, shell, Python, etc).

Skilled in verification techniques, and timing/stability analysis.

Proficiency in understanding PCB designs and reading schematics.

Proficiency in understanding embedded software.

Knowledge of ADC/DAC interfaces and JESD204.

Expertise in implementing high speed digital communications interfaces.

Demonstrated success working in a dynamic environment.

Master’s degree in Computer Engineering, Electrical Engineering, or equivalent.

Experience designing for space environments including radiation impacts and mitigation.

Proficiency with lab tools and working with hardware.

Familiarity with SystemRDL.

Familiarity with Model Based Design methodologies

Understanding of OVM/UVM framework and methodology.

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