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Senior DV Engineer
espace Saratoga, CA
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Ghost-risk verdict
Some ghost-posting signals
- open for 87 days (60–89 days is elevated risk)
- 123 open roles at this company in 30 days (mass-hiring blitz)
- no salary disclosed (correlates with ghost postings)
See your fit for this role and apply with a truthfully tailored résumé.
About the role
Requirements
HDL & Verification Methodology
· Proficiency in Verilog and SystemVerilog
· Working knowledge of UVM architecture and methodology
· Ability to write verification tests within an existing environment
Programming & Scripting
· Some experience scripting in Perl, Python, or bash
What you bring to this role:
4+ years of design verification experience in the semiconductor industry
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