FPGA / VLSI Engineer

Responsibilities:

Design and implement RTL using SystemVerilog with consideration for timing, power, and area

Perform FPGA prototyping, validation, and hardware bring-up for digital designs

Develop and execute simulation and debugging strategies at block and subsystem levels

Contribute to SoC-level integration, including interfacing with processors, memory, and peripherals

Analyze and resolve timing issues, including setup/hold violations and basic clock domain crossing concerns

Collaborate with verification, ASIC, and software teams to ensure functional correctness and performance

Participate in design reviews and contribute to improving design quality and best practices

Qualifications:

Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field

Strong experience writing synthesizable SystemVerilog/Verilog

Proven experience with FPGA development flows, including synthesis, implementation, and validation

Solid understanding of digital design fundamentals and timing analysis

Preferred Skills:

Experience with SoC FPGA platforms (e.g., Xilinx Zynq, Intel SoC FPGA)

Familiarity with AXI/AHB or similar bus protocols

Exposure to ASIC design flow, including synthesis and STA

Experience with high-speed interfaces (e.g., PCIe, Ethernet)

Knowledge of communication systems (e.g., 5G PHY/MAC concepts)

What Success Looks Like:

Independently handles well-defined design blocks from RTL to FPGA validation

Produces clean, efficient, and timing-aware RTL

Effectively debugs issues across simulation and hardware

Collaborates well within a team and contributes to overall project progress

Continuously improves technical depth and delivery efficiency